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Data Sheet
register is set to 1. To find the phase that triggered the interrupt,
one of either the IPEAK or VPEAK registers is read immediately
after reading the STATUS1 register. Next, the status bits are
cleared, and the IRQ1 pin is set to high by writing to the
STATUS1 register with the status bit set to 1.
Note that the internal zero-crossing counter is always active. By
setting Bits[4:2] (PEAKSEL[2:0]) in the MMODE register, the
first peak detection result is, therefore, not executed across a full
ADE7880
Whenever the absolute instantaneous value of the voltage goes
above the threshold from the OVLVL register, Bit 18 (OV) in
the STATUS1 register and Bit 9 (OVPHASE[0]) in the PHSTATUS
register are set to 1. Bit 18 (OV) of the STATUS1 register and
Bit 9 (OVPHASE[0]) in the PHSTATUS register are cancelled
when the STATUS1 register is written with Bit 18 (OV) set to 1.
The recommended procedure to manage overvoltage events is
the following:
PEAKCYC period. Writing to the PEAKCYC register when the
PEAKSEL[2:0] bits are set resets the zero-crossing counter,
thereby ensuring that the first peak detection result is obtained
across a full PEAKCYC period.
Overvoltage and Overcurrent Detection
The ADE7880 detects when the instantaneous absolute value
measured on the voltage and current channels becomes greater
than the thresholds set in the OVLVL and OILVL 24-bit
unsigned registers. If Bit 18 (OV) in the MASK1 register is set,
the IRQ1 interrupt pin is driven low in case of an overvoltage
1.
2.
3.
4.
5.
Enable OV interrupts in the MASK1 register by setting
Bit 18 (OV) to 1.
When an overvoltage event happens, the IRQ1 interrupt
pin goes low.
The STATUS1 register is read with Bit 18 (OV) set to 1.
The PHSTATUS register is read, identifying on which
phase or phases an overvoltage event happened.
The STATUS1 register is written with Bit 18 (OV) set to 1.
In this moment, Bit OV is erased and also all Bits[11:9]
(OVPHASE[2:0]) of the PHSTATUS register.
event. There are two status flags set when the IRQ1 interrupt
pin is driven low: Bit 18 (OV) in the STATUS1 register and one
of Bits[11:9] (OVPHASE[2:0]) in the PHSTATUS register to
identify the phase that generated the overvoltage. The Status
Bit 18 (OV) in the STATUS1 register and all Bits[11:9]
(OVPHASE[2:0]) in the PHSTATUS register are cleared, and
the IRQ1 pin is set to high by writing to the STATUS1 register
with the status bit set to 1. Figure 60 presents overvoltage
detection in the Phase A voltage.
In case of an overcurrent event, if Bit 17 (OI) in the MASK1
register is set, the IRQ1 interrupt pin is driven low. Immediately,
Bit 17 (OI) in the STATUS1 register and one of Bits[5:3]
(OIPHASE[2:0]) in the PHSTATUS register, which identify
the phase that generated the interrupt, are set. To find the
phase that triggered the interrupt, the PHSTATUS register
is read immediately after reading the STATUS1 register. Next,
Status Bit 17 (OI) in the STATUS1 register and Bits[5:3]
(OIPHASE[2:0]) in the PHSTATUS register are cleared and the
PHASE A
VOLTAGE CHANNEL
OVLVL[23:0]
OVERVOLTAGE
DETECTED
IRQ1 pin is set to high by writing to the STATUS1 register with
the status bit set to 1. The process is similar with overvoltage
detection.
Overvoltage and Overcurrent Level Set
The content of the overvoltage (OVLVL), and overcurrent,
(OILVL) 24-bit unsigned registers is compared to the absolute
value of the voltage and current channels. The maximum value of
these registers is the maximum value of the HPF outputs:
+5,326,737 (0x514791). When the OVLVL or OILVL register is
equal to this value, the overvoltage or overcurrent conditions
BIT 18 (OV) OF
STATUS1
BIT 9 (OVPHASE)
OF PHSTATUS
STATUS1[18] AND
PHSTATUS[9]
CANCELLED BY A
WRITE OF STATUS1
WITH OV BIT SET.
Figure 60. Overvoltage Detection
are never detected. Writing 0x0 to these registers signifies the
overvoltage or overcurrent conditions are continuously
detected, and the corresponding interrupts are permanently
triggered.
As stated in the Current Waveform Gain Registers section, the
serial ports of the ADE7880 work on 32-, 16-, or 8-bit words.
Similar to the register presented in Figure 57, OILVL and
OVLVL registers are accessed as 32-bit registers with the eight
MSBs padded with 0s.
Rev. A | Page 35 of 104
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